Verilog introductory course

Introduction to Digital Design and Synthesis with Verilog HDL

2 days

Goal

After the workshop you will understand the structure of the Verilog language and
strategies for writing code for synthesis. You will also after the workshop be able to
start writing code for real designs.

Designed for

FPGA/PLD Designers who traditionally have used VHDL and need to evaluate
Verilog HDL.
Engineers and project leaders evaluating Verilog HDL.
Engineers who are going to work with Verilog HDL, but are in an early design
phase.

Prerequisites

Some knowledge of issues in digital hardware design.

Main Topics Covered

Introduction:

Open Verilog International, General HDL concepts and Verilog HDL applications.

Language introduction:

The module, Common data types and operators, Concurrency, Procedural Statements, Timing Control,
Built-In functions and Compiler directives.

Data types and operators:

nets, registers, parameters, named events and port rules.

Synthesis introduction:

The RTL concept, Register Inference, Synthesis of different Verilog HDL constructs, FSM for synthesis,
Unsupported Verilog HDL constructs.

Free Simulator

Continue with the labs at home with a free PC/Mac based Verilog HDL Simulator.

Course Dates

Public course dates: On request.
On-site course dates: Are arranged together with the Customer.

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