Verilog extensive course -

Advanced Digital Design and Synthesis with Verilog HDL

2 days

Goal

After the workshop you have knowledge of all important language constructs, how to
write automated test procedures for simulation and how to use LAI-models in the
simulation environment.

Designed for

FPGA/ASIC designers.
Engineers who are going to create behavioral models for use in the Verilog HDL
environment.
Engineers who are going to work with Verilog HDL as a simulation tool.

Prerequisites

Previous knowledge of Verilog HDL corresponding to the workshop “Introduction to
Digital Design and Synthesis with Verilog HDL”.

Main Topics Covered

Procedural Timing Control:

Simple delay, edge and level timing control and intra assignment timing control.

Procedural Statements:

Assignments, non-blocking assignments, continuous procedural assignments, force and release and
if-case-casex-casez-while-repeat-for-forever statements.

Functions and Tasks:

Definitions, function call, function return value, task enabling, task disabling, rules and built-in functions
and tasks for file i/o.

Named Blocks:

Sequential and parallel blocks and disabling of named blocks.
Gate Level Timing and Specify Block:
Delay specification, gate and net delay and specify blocks including built-in timing control functions.

Free Simulator:

Continue with the labs at home with a free PC/Mac based Verilog HDL
Simulator.

Course Dates

Public course dates: On request.
On-site course dates: Are arranged together with the Customer.

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